The Verification Adventures Blog This blog will hosting several articles about Design and Verification projects. Here is a list of the main HDL languages and tools delployed: Systemveriglog as main RTL design code Python (Cocotb and Pyuvm) as main verification environment Verilator as main Simulator for both GLS and standard RTL simulation Yosys and Sby as Synth and Formal tooling SystemRDL and PYUVM ral as main register flow Here is instead a list of projects I’m and I have been working on for a while PYUVM RAL: ENIGMA MACHINE DMG (Game Boy first Edition) Z80 CPU (Zilog) RISCV and Tiny RISCV all this projects are deployed when possible on an Icesugar / Icebreaker using the ICE40 open source tools....